1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device supporting a training mode and a semiconductor system with the same.
2. Description of the Related Art
A semiconductor device becomes more integrated and of higher speed depending on demands. A semiconductor device uses a plurality of clocks according to target elements due to a high-speed operation.
For example, a dynamic random access memory (DRAM) uses a data clock and a command clock, which synchronizes a command. That is, a memory device such as the DRAM receives or outputs data using the data clock, and receives a command and an address using the command clock. The data clock has a high frequency, for example 2 GHz, and the command clock has a relatively lower frequency, for example, 1 GHz. A high-speed memory device with an operation speed of 4 Gbps is realized with the data clock and the command clock.
When the plurality of clocks are not synchronized or arranged, the semiconductor device cannot perform normal operations due to a time skew between the clocks. The semiconductor device performs a training mode in order to arrange or synchronize the plurality of clocks. The training mode is a process of training before entering a normal mode for optimized operation performance in the normal mode.
The training mode will be described with a conventional memory device as an example.
FIG. 1 is a block diagram illustrating a conventional memory device.
Referring to FIG. 1, the conventional memory device 10 includes a command pad HCK, a command clock buffer unit 11, a data pad WCK, a data clock input unit 13, a phase information provision unit 15, and a phase information pad EDC.
An external command clock eHCK having a low frequency, for example 1 GHz, is received through the command pad HCK. The command clock buffer unit 11 generates an internal command clock iHCK in response to the external command clock eHCK. An external data clock eWCK having a high frequency, for example 2 GHz, is received through the data pad WCK. The data clock input unit 13 generates an internal data division clock iWCK_DVD having the same frequency as the internal command clock iHCK in response to the external data clock eWCK. The phase information provision unit 15 generates a phase information signal ePD between the internal command clock iHCK and the internal data division clock iWCK_DVD in response to a training mode signal TM. The phase information pad EDC outputs the phase information signal ePD to the external device.
The data clock input unit 13 includes a data clock buffer unit 13A and a dividing unit 13B.
The data clock buffer unit 13A generates an internal data clock iWCK in response to the external data clock eWCK. The dividing unit 13B generates the internal data division clock iWCK_DVD by dividing the internal data clock iWCK. The internal data division clock iWCK_DVD is one of first to fourth internal data division clocks (not illustrated) respectively corresponding to 4 phases of 0°, 90°, 180° and 270° to the internal data clock iWCK.
The phase information provision unit 15 includes a replica delay unit 15A, a phase comparing unit 15B and an output driver unit 15C.
The replica delay unit 15A outputs a delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by a preset delay amount. The phase comparing unit 15B compares phases of the delay division clock iWCK_DLY and the internal command clock iHCK. The output driver unit 15C drives a phase comparison signal iPD output from the phase comparing unit 15B to the phase information pad EDC.
The replica delay unit 15A is provided in order to synchronize an internal delay amount reflected in the internal command clock iHCK with an internal delay amount reflected in the internal data division clock iWCK_DVD. Even though not illustrated in FIG. 1, the internal delay amount reflected in the internal command clock iHCK is greater than the internal delay amount reflected in the internal data division clock iWCK_DVD. If the internal delay amount reflected in the internal command clock iHCK is less than the internal delay amount reflected in the internal data division clock iWCK_DVD, the replica delay unit 15A would be disposed on a transmission line of the internal command clock iHCK.
An operation of the memory device 10 will be described with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating a training process of the conventional memory device 10.
Referring to FIG. 2, an external controller (not illustrated) generates and provides the external command clock eHCK and the external data clock eWCK to the conventional memory device 10 at an initial operation. The conventional memory device 10 internally generates the internal command dock iHCK corresponding to the external command clock eHCK and the internal data division clock iWCK_DVD corresponding to the external data dock eWCK and enters the training mode under the control of the external controller.
After entering the training mode in response to an activation of the training mode signal TM, the conventional memory device 10 samples one of the internal command clock iHCK and the internal data division clock iWCK_DVD based on the other one of the internal command clock iHCK and the internal data division clock iWCK_DVD, and generates and provides the phase information signal ePD in response to a sampling result to the external controller.
In detail, the replica delay unit 15A outputs the delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by the preset delay amount. The phase comparing unit 15B compares the phases of the delay division clock iWCK_DLY and the internal command clock iHCK and outputs the phase comparison signal iPD in response to the comparison result. The output driver unit 15C drives the phase information signal ePD corresponding to the phase comparison signal IPD to the phase information pad EDC.
For example, the phase comparing unit 15B generates the phase comparison signal iPD of a logic high level or a logic low level according to a phase relationship between the delay division clock iWCK_DLY and the internal command clock iHCK, and the output driver unit 15C provides the phase information signal ePD of the logic high level or the logic low level to the external controller through the phase information pad EDC in response to the phase comparison signal iPD.
The external controller adjusts one of phases of the external command clock eHCK and the external data clock eWCK in response to the phase information signal ePD. For example, the external controller shifts the phase of the external data clock eWCK backward when the phase of the delay division clock iWCK_DLY leads the phase of the internal command clock iHCK, and shifts the phase the external data clock eWCK forward when the phase of the internal command clock iHCK leads the phase of the delay division clock iWCK_DLY.
The process of moving forward and backward is repeated until the phases of the Internal command clock iHCK and the delay division clock iWCK_DLY are identical to each other. For example, the external controller shifts backward the phase of the external data clock eWCK by a preset amount of level when the phase of the delay division clock iWCK_DLY leads the phase of the internal command clock iHCK, and then stops the training operation when the phase of the internal command clock iHCK leads the phase of the delay division clock iWCK_DLY.
Accordingly, optimal operation circumstance in the normal mode may be provided to the memory device 10 by making the phases of the internal command clock iHCK and the delay division clock iWCK_DLY identical to each other.
However, the conventional memory device 10 has a concern as follows.
The memory device 10 generates the phase information signal ePD according to the phase relationship between the delay division clock iWCK_DLY corresponding to the external data clock eWCK and the internal command clock iHCK corresponding to the external command clock eHCK. The memory device 10 provides simple phase information denoting which one of phases of the Internal command clock iHCK and the delay division clock iWCK_DLY leads to the other, and generates the phase information signal ePD of single bit having the logic high level or the logic low level.
The external controller adjusts one of the phases of the external command clock eHCK and the external data clock eWCK in response to the phase information signal ePD. The external controller adjusts one of the phases of the external command clock eHCK and the external data clock eWCK step by step by the preset amount of level, which means that there are more steps to adjust one of the phases of the external command clock eHCK and the external data clock eWCK as a phase difference between the external command clock eHCK and the external data clock eWCK becomes greater. Thus, there needs more time for the training operation as the phase difference between the external command clock eHCK and the external data clock eWCK becomes greater.